基于FPGA的SOPC自定义IP核的设计

doi:10.3969/j.issn.1006-2475.2010.08.014

计算机与现代化 ›› 2010, Vol. 1 ›› Issue (8): 47-51.doi: 10.3969/j.issn.1006-2475.2010.08.014

基于FPGA的SOPC自定义IP核的设计

李向东¹，胡怀伟²，郝陆军¹，闫新分¹

1.河南省安彩高科股份有限公司动力厂电气车间，河南安阳 455000； 2.西安工程大学电子信息学院，陕西西安 710048

收稿日期:2010-01-18 修回日期:1900-01-01 出版日期:2010-08-27 发布日期:2010-08-27

Design of Custom IP Core in SOPC Based on FPGA

LI Xiang-dong¹, HU Huai-wei², HAO Lu-jun¹, YAN Xin-fen¹

1.Department of Electric Workshop, Anyang AC Company, Anyang 455000, China;2.Department of Electrical Engineering， Xi’an Polytechnic University, Xi’an 710048， China

Received:2010-01-18 Revised:1900-01-01 Online:2010-08-27 Published:2010-08-27

摘要/Abstract

摘要： 基于FPGA的SOPC设计技术是当前电子设计领域的最前沿技术之一，自定义IP核是SOPC系统灵活性的重要体现，是SOPC系统设计的重中之重。本文以ALtera公司Cyclone系列的EP1C6Q240C8为例详细阐述用户自定义IP核设计方法及其使用SOPC Builder开发的流程，并在此基础上开发出七段数码管 (LED)的自定义IP核。在Quartus II8.0环境下, 用Verilog实现LED的硬件设计；在NiosⅡIDE环境下,基于C语言开发LED的软件应用程序接口(API)函数来访问和控制硬件。

关键词: NiosⅡ, 自定义IP 核, Avalon总线, 设备驱动

Abstract: The FPGA based on the SOPC is one of the last technologies in electronic design fields. Custom IP core is the important embodiment of the SOPC system flexibility, and is most important in the design of the SOPC system. This paper describes the design of custom IP core and the design flow using SOPC Builder, taking EP1C6Q240C8 for example that belongs to Cyclone series made by ALtera Co. On the condition of Quartus II8.0, the hardware of sevenLED is designed by Verilog language. On the condition of NiosⅡIDE, the API to access and control the hardware equipment is developed by C language.

Key words: NiosⅡ, custom IP core, Avalon bus, device driver

李向东;胡怀伟;郝陆军;闫新分. 基于FPGA的SOPC自定义IP核的设计[J]. 计算机与现代化, 2010, 1(8): 47-51.

LI Xiang-dong;HU Huai-wei;HAO Lu-jun;YAN Xin-fen. Design of Custom IP Core in SOPC Based on FPGA[J]. Computer and Modernization, 2010, 1(8): 47-51.

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基于FPGA的SOPC自定义IP核的设计

Design of Custom IP Core in SOPC Based on FPGA

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